Methods and structures disclosed herein relate to far back end of the line (FBEOL) metallization during integrated circuit chip manufacturing.
Recently, in an attempt to save on costs, aluminum has been replaced with copper in far back end of line (FBEOL) metallization during integrated circuit chip manufacturing. Specifically, copper has been used instead of aluminum during FBEOL metallization to form metal pads for solder bumps used in controlled collapsed chip connections (C4 connections) (referred to herein as under-bump pads or to herein as solder bump pads) and to simultaneously form additional metal features, such as metal pads for providing electrical access to on-chip devices (e.g., for providing electrical connections between on-chip devices and a printed circuit board (PCB)) (referred to herein as wirebond pads), metal pads for providing electrical access to kerf region (i.e., scribe line) test structures (referred to herein as probe pads), and final (i.e., uppermost) vertical sections of crackstop structures, which extend vertically from the final metallization layer down to the active device layer and border the chips in order to inhibit damage during wafer dicing and chip packaging. Unfortunately, current FBEOL metallization techniques for forming both under-bump pads and additional metal features using copper are not optimal because the surface and bulk copper of the additional metal features is left exposed during subsequent wafer finishing processes (e.g., C4 connection formation processes), thereby leaving such additional metal features at risk of processing-related defects (e.g., etch back, oxidation, etc.), which could impact their final integrity, if development and manufacturing-level optimization activity does not fully succeed.